1. Field of the Invention
The present invention relates to a solid-state imaging device which may typically be a CMOS image sensor and to a camera system having such a device.
2. Description of the Related Art
Recently, increasing attention is paid to CMOS image sensors which are regarded as solid-state imaging devices (image sensors) to replace CCDs.
The manufacture of CCD pixels necessitates dedicated processes, and a plurality of power supply voltages are required to operate the pixels. Further, the pixels must be driven by a plurality of peripheral ICs operating in combination.
Under the circumstance, CMOS image sensors are regarded advantageous because problems including high complicatedness of such a driving system are overcome in CMOS image sensors.
A CMOS image sensor can be manufactured using manufacturing processes similar to those used for common CMOS integrated circuits. A CMOS image sensor can be driven by a single power source, and it can be consolidated with analog circuits and logic circuits manufactured using CMOS processes into a single chip.
As thus described, a CMOS image sensor provides a plurality of significant advantages such as a reduction in the number of peripheral ICs required.
The main stream of CCD output circuits is one-channel type circuits utilizing an FD amplifier including a floating diffusion layer.
On the contrary, CMOS image sensors include an FD amplifier provided at each pixel, and the main stream of such sensors is column-parallel output type sensors. That is, pixels of one selected row of pixels in a pixel array of such a sensor are simultaneously read out in the direction in which pixel columns are arranged (column direction).
It is difficult to provide sufficient driving capability with an FD amplifier provided at each pixel, and the data rate must therefore be reduced in this case. Parallel processing is regarded advantageous for such a reason.
Various circuits have been proposed as pixel signal readout (output) circuits for column-parallel output type CMOS image sensors. One of the most advanced mode of such circuits is a type of circuits in which an analog-digital converter (hereinafter abbreviated as “ADC”) is provided at each column of pixels to obtain a pixel signal as a digital signal.
For example, CMOS image sensors incorporating such column-parallel type ADCs are disclosed in W. Yang et al., “An Integrated 800×600 CMOS Image System” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 (Non-Patent Document 1) and JP-A-2005-278135 and JP-A-2005-323331 (Patent Documents 1 and 2).
FIG. 1 is a block diagram of a solid-state imaging device (CMOS image sensor) having column-parallel type ADCs showing an exemplary configuration thereof.
As shown in FIG. 2, a solid-state imaging device 10 includes a pixel section 11 serving as an imaging section, a vertical scan circuit 12, a horizontal transfer scan circuit 13, a timing control circuit 14, an ADC group 15, a digital-analog converter (hereinafter abbreviated as “DAC”) 16, a sense circuit 17, and a signal processing circuit 18.
The pixel section 11 is formed by unit pixels PXL disposed in the form of a matrix, each unit pixel including a photodiode and an in-pixel amplifier.
The solid-state imaging device 10 also includes control circuits for sequentially reading out signals from the pixel section 11. The control circuits include the timing control circuit 14 which generals an internal clock, the vertical scan circuit 12 which controls row addressing and row scanning, and the horizontal transfer scan circuit 13 which controls column addressing and column scanning.
The ADC group 15 include comparators 15-1 each of which compares a reference voltage Vslop that is a ramp waveform (RAMP) obtained by varying stepwise a reference voltage generated by the DAC 16 with an analog signal obtained from a pixel on each row of pixels via a vertical signal line.
The ADC group 15 is formed by a plurality of columns of ADCs each including a comparator 15-1, a counter 15-2 counting the time of comparison performed by the comparator 15-1, and a latch (memory device) 15-3 holding the result of the counting.
The ADC group 15 has the function of converting a signal into an n-bit digital signal, and one ADC is disposed in association with each vertical signal line (column line) to form a column-parallel ADC block.
The output of each latch 15-3 is connected to a n-bit wide horizontal transfer line 19.
In association with the horizontal transfer line 19, n sense circuits 17 and a signal processing circuit 18 are provided.
FIG. 2 is a circuit diagram of such a comparator showing an exemplary configuration thereof.
A comparator 15-1 is configured as a common differential amplifier formed by PMOS transistors PT1 and PT2 and NMOS transistors NT1 and NT2.
Capacity elements C1 and C2 are connected in series to gate terminals of the transistors NT1 and NT2 serving as an input portion of the comparator, and an input signal is input to the comparator with DC components removed from the signal.
Reset switches SW1 and SW2 are also provided for setting an initial operating voltage.
Operations of the CMOS image sensor 10 shown in FIG. 1 will now be described with reference to the timing chart shown in FIG. 3.
After the readout of a reset level from the unit pixels PXL on an arbitrary row Vx to column lines H0, H1, . . . is stabilized (time t8), the comparators 15-1 are reset by a reset signal PSET for the comparators 15-1.
Such an operation allows any variation of the reset level at each pixel and any offset voltage of the relevant comparator to be memorized or absorbed by the capacity elements C1 and C2.
Next (time t10), a sloped waveform resulting from a time-dependent change in the reference voltage RAMP (Vslop) is input from the DAC 16, and the waveform is compared with a voltage from an arbitrary column line Hx at the relevant comparator 15-1.
When the sloped waveform is input, first counting is carried out by the counter 15-2 simultaneously and in parallel with the input of the sloped waveform. The counter 15-2 carries out the counting in a decremental mode.
When the reference voltage RAMP and the voltage from the arbitrary column line Hx equals each other, the output of the comparator 15-1 is inverted, and a count corresponding to the period of counting is held in the counter 15-2.
Since the first conversion is the conversion of a reset level of the pixels, values that the signal can assume is limited in a rather small range, the conversion requires a conversion time shorter than that required for second conversion.
Second readout is carried out to read out a signal component according to the amount of light incident on the unit pixel PXL, and the signal component is converted through an operation that is similar to the first readout. At this time, the counter 15-2 carries out incremental counting.
When the reference voltage RAMP and the voltage from the column line Hx equal each other, the output of the comparator 15-1 is inverted again (time t22). At this time, the counter holds a difference between the result of the second conversion and the result of the first conversion, i.e., the conversion of the reset level.
This example of the related art is significantly characterized in that CDS is carried out as thus described.
After the A-D conversion period terminates as thus described, the data in the counters are saved in the memories 15-3, and the A-D converters start A-D conversion of the next row Vx+1.
In the mean time, the data in a memory 256 are sequentially selected by the horizontal transfer scan circuit 13 and read out using the sense circuit 17.
According to the A-D conversion method which is typically illustrated in FIG. 1, the resolution of A-D conversion (the magnitude of 1 LSB) is determined by the counting speed of the counter 15-2 during a change in the reference voltage RAMP and the slope of the reference voltage RAMP.
The conversion method will be described in detail with reference to FIG. 4.
FIG. 4 is an enlarged view of the reset component converting part of FIG. 3.
Let us assume that the time required for a counter to increment or decrement its count will be referred to as “count cycle”. Then, the amount of a change in the reference voltage RAMP during a count cycle is the resolution of an A-D converter (the magnitude of 1 LSB).
When the reference voltage has a steep slope as represented by the solid line, the width of 1 LSB is great. When the reference voltage has a gentle slope as represented by the broken line, the width of 1 LSB is smaller.
Controlling the width of 1 LSB by changing the slope of the voltage is equivalent to controlling the readout gain.